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iN82C55AN 1 chmos programmable peripheral interface the integral iN82C55AN is a high-performance, chmos version of the industry standard iN82C55AN general purpose programmable i/o dev ice which is designed for use with all intel and most other microprocessors. it prov ides 24 i/o pins which may be individually programmed in 2 groups of 12 and used in 3 major modes of operation. in mode 0, each group of 12 i/o pins may be pr ogrammed in sets of 4 and 8 to be inputs or outputs. in mode 1, each group may be progr ammed to have 8 lines of input or output. 3 of the remaining 4 pins are used for handshaking and interrupt control signals. mode 2 is a strobed bi-directional bus configuration. features ? compatible with all intel and most other microprocessors ? high speed, ?zero wait state? o peration with 8mhz 8086/88 and 80186/188 ? 24 programmable i/o pins ? low power chmos ? completely ttl compatible ? control word read-back capability ? direct bit set/reset capability ? 2.5ma dc drive capability on all i/o port outputs ? available in 40-pin dip ? available in express ? standard temperature range ? extended temperature range group a control data bus buffer read/ write control logic group b control group b port b (8) group b port c lower (4) group a port c upper (4) group a port a (8) pa 7 -pa 0 pc 7 -pc 4 pc 3 -pc 0 pb 7 -pb 0 d 7 -d 0 rd rd wr cs a 1 a 0 reset 8 bit internal data bus figure 1 1. 2. 3. 4. 5. 6. 7. 8. 9. 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 pa 4 pa 5 pa 6 pa 7 wr reset d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 v cc pb 7 pb 6 pb 5 pb 4 pb 3 pa 3 pa 2 pa 1 pa 0 rd cs v ss a 1 a 0 pc 7 pc 6 pc 5 pc 4 pc 0 pc 1 pc 2 pc 3 pb 0 pb 1 pb 2 figure 2
iN82C55AN 2 symbol pin number type name and function pa 3-0 1-4 i/o port a, pins 0-3: lower nibble of an 8-bit data output latch buffer and an 8-bit data input latch. r d 5 i read control: this input is low during cpu read operations. cs 6 i chip select: a low on this input enables the 82c55a to respond to r d and wr signals rd and wr are ignored otherwise. gnd 7 system ground. a 1-0 8-9 i address: these input signals in conjunction r d and wr control the selection of one of the three ports or the control word registers. a 1 a 0 r d wr cs input operation (read) 0 0 0 1 0 port a - data bus 0 1 0 1 0 port b - data bus 1 0 0 1 0 port c - data bus 1 1 0 1 0 control word - data bus output operation (write) 0 0 1 0 0 data bus - port a 0 1 1 0 0 data bus - port b 1 0 1 0 0 data bus - port c 1 1 1 0 0 data bus ? control disable function x x x x 1 data bus-3-state x x 1 1 0 data bus-3-state pc 7-4 10-13 i/o port c, pins 4-7: upper nibble of an 8-bit data output latch/buffer and an 8-bit data input buffer (no latch for input). this port can be divided into two 4-bit ports under the mode control. each 4-bit port contains a 4-bit latch and it can be used for the control signal outputs and status signal inputs in conjunction with ports a and b. pc 0-3 14-17 i/o port c, pins 0-3: lower nibble of port c. pb 0-7 18-25 i/o port b, pins 0-7: an 8-bit data output latch/buffer and an 8- bit data input buffer vcc 26 system power: +5v power supply d 7-0 27-34 i/o data bus: bi-directional, tri-state data bus lines, connected to system data bus reset 35 i reset: a high on this input clears the control register and all ports are set to the input mode wr 36 i write control: this input is low during cpu write operations pa 7-4 37-40 i/o port a pins 4-7: upper nibble of an 8-bit data output latch/buffer and an 8-bit data input latch
iN82C55AN 3 in 82c55an functional description general the iN82C55AN is a programmable peripheral interfac e device designed for use in intel microcomputer systems. its function is that of a general purpose i/o component to interface peripheral equipment to the microcomputer system bus. the func tional configuration of the in82c55a n is programmed by the system software so that normally no external logic is necessa ry to interface peripheral devices or structures. data bus buffer this 3-state bidirectional 8-bit buffer is used to in terface the iN82C55AN to the system data bus. data is transmitted or received by the buffer upon execution of input or output in structions by t he cpu. control words and status information are also transferred through the data bus buffer. read/write and control logic the function of this block is to manage all of the inte rnal and external transfers of both data and control or status words. it accepts inputs fr om the cpu address and control busses and in turn, issues commands to both of the control groups. group a and group b controls the functional configuration of each port is programm ed by the systems software. in essence, the cpu ?outputs? a control word to the in82c 55an. the control word contains info rmation such as ?mode?, ?bit set?, ?bit reset?, etc., that initializes the functional configuration of the 82c 55a. each of the control blocks (group a and group b) accepts ?commands? from the read/write control logic, receives ?control words? from the internal data bus and issues the proper commands to its associated ports. control group a - port a and port c upper (c7 - c4) control group b - port b and port c lower (c3 - c0) the control word register can be both written and r ead as shown in the address decode table in the pin descriptions. figure 6 shows the control word format for both read and write operations. when the control word is read, bit d7 will always be a logic ?1?, as this implies control word mode information. ports a, b, and c the iN82C55AN contains three 8-bit por ts (a, b, and c). all can be configured in a wide variety of functional characteristics by the system softw are but each has its own special feat ures or ?personality? to further enhance the power and flexibility of the iN82C55AN. port a. one 8-bit data output latch/buffer and one 8-bit input latch/buffer. both ?pull-up? and ?pull-down? bus hold devices are present on port a. port b. one 8-bit data input/output latch/buffer. only ? pull-up? bus hold devices are present on port b. port c. one 8-bit data output latch/buffer and one 8-bit data i nput buffer (no latch for input). this port can be divided into two 4-bit ports under the mode control. each 4-bit port contains a 4-bit latch and it can be used for the control signal outputs and status signal inputs in conjunction with ports a and b. only ?pull-up? bus hold devices are present on port c. see figure 4 for the bus-hold circuit c onfiguration for port a, b, and c.
iN82C55AN 4 group a control data bus buffer read/ write control logic group b control group b port b (8) group b port c lower (4) group a port c upper (4) group a port a (8) pa 7 -pa 0 pc 7 -pc 4 pc 3 -pc 0 pb 7 -pb 0 d 7 -d 0 rd rd wr cs a 1 a 0 reset 8 bit internal data bus figure 3. iN82C55AN block diagram showing da ta bus buffer and read write control logic functions reset internal data in internal data out internal data out externa l port a pin reset internal data out vcc p* wr externa l port b,c pin *note: port pins loaded with more than 20pf capacitance may not have their logic level guaranteed following a hardware reset. * wr figure 4. port a, b, c, bus-hold configuration
iN82C55AN 5 iN82C55AN operational description mode selection there are three basic modes of operation that can be selected by the system software: mode 0 - basic input/output mode 1 - strobed input/output mode 2 - bi-directional bus when the reset input goes ?high? all ports will be set to the input mode with all 24 port lines held at a logic ?one? level by the internal bus hold devices (see figur e 4 note). after the reset is removed the iN82C55AN can remain in the input mode with no additional initializ ation required. this eliminates the need for pullup or pulldown devices in ?all cmos? designs. during the ex ecution of the system pr ogram, any of the other modes may be selected by using a single output instruct ion. this allows a single iN82C55AN to service a variety of peripheral devices with a simple software maintenance routine. the modes for port a and port b can be separately defi ned, while port c is divided into two portions as required by the port a and port b definitions. all of the output registers, including t he status flip-flops, will be reset whenever the mode is changed. modes may be comb ined so that their functional definition can be ?tailored? to almost any i/o struct ure. for instance; group b can be programmed in mode 0 to monitor simple switch closings or display computational results, group a could be programmed in mode 1 to monitor a keyboard or tape reader on an interrupt-driven basis. adress bus 8 rd, wr d7-d0 a0, a1 bca control bus data bus 8 4 4 8 mode 0 pb 7 -pb 0 pc 3 -pc 0 pc 7 -pc 4 pa 7 -pa 0 8 8 mode 1 pb 7 -pb 0 contro l or i/o control or i/o pa 7 -pa 0 bca 8 8 mode 2 pb 7 -pb 0 i/o control pa 7 -pa 0 bca figure 5. basic mode definitions and bus interface
iN82C55AN 6 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 group b port c (lower) 1 = input 0 = output port b 1 = input 0 = output mode selection 0 = mode 0 1 = mode 1 group b port c (lower) 1 = input 0 = output port b 1 = input 0 = output mode selection 00 = mode 0 01 = mode 1 1x = mode 2 mode set flag 1 = active figure 6. mode definition format the mode definitions and possible mode combinations may s eem confusing at first but after a cursory review of the complete device operation a simple, logical i/o approach will surface. the design of the 82c55a has taken into account things such as efficient pc boar d layout, control signal definition vs pc layout and complete functional flexibility to support almost any per ipheral device with no external logic. such design represents the maximum use of the available pins. single bit set/reset feature any of the eight bits of port c can be set or reset us ing a single output instruct ion. this feature reduces software requirements in control-based applications. when port c is being used as status/control for port a or b, these bits can be set or reset by using the bit set/reset operation just as if they were data output ports. d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 bit set/reset 1 = set 0 =reset bit select 01234567 01010101b 0 00110011b 1 00001111b 2 bit set/reset flag 0 = active don?t care figure 7. bit set/reset format
iN82C55AN 7 interrupt control functions when the iN82C55AN is programmed to operate in mode 1 or mode 2, control signal s are provided that can be used as interrupt request inputs to the cpu. the interrupt request signals, generated from port c, can be inhibited or enabled by setting or resetting the associated inte flip-flop, using the bit set/reset function of port c. this function allows the programmer to disallow or allo w a specific i/o device to interrupt the cpu without affecting any other device in the interrupt structure. inte flip-flop definition: (bit-set) - inte is set - interrupt enable (bit-reset) ? inte is reset - interrupt disable note: all mask flip-flops are automatically re set during mode selection and device reset. operating modes mode 0 (basic input/output). this functional configuration provides simple input and output operations for each of the three ports. no ?handshaking? is required, data is simply writt en to or read from a specified port. mode 0 basic functional definitions: ? two 8-bit ports and two 4-bit ports. ? any port can be input or output. ? outputs are latched. ? inputs are not latched. ? 16 different input/output configurat ions are possible in this mode. mode 0 (basic input) t rr t ir t hr t ar t ra t rd t df rd input cs, a 1 , a 0 d 7 -d 0
iN82C55AN 8 mode 0 (basic output) t ww t dw t wd t wa t aw t wb wr d 7 -d 0 cs ,a1,a0 output mode 0 port definition a b group a group b d4 d3 d1 d0 port a port c (upper) # port b port c (lower ) 0 0 0 0 output outpu t 0 outpu t outpu t 0 0 0 1 output outpu t 1 outpu t input 0 0 1 0 output outpu t 2 input outpu t 0 0 1 1 output outpu t 3 input input 0 1 0 0 output input 4 outpu t outpu t 0 1 0 1 output input 5 outpu t input 0 1 1 0 output input 6 input outpu t 0 1 1 1 output input 7 input input 1 0 0 0 input outpu t 8 outpu t outpu t 1 0 0 1 input outpu t 9 outpu t input 1 0 1 0 input outpu t 10 input outpu t 1 0 1 1 input outpu t 11 input input 1 1 0 0 input input 12 outpu t outpu t 1 1 0 1 input input 13 outpu t input 1 1 1 0 input input 14 input outpu t 1 1 1 1 input input 15 input input
iN82C55AN 9 mode 0 configurations control word #0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 10000000 a c? b 8 4 4 8 pa 7 -pa 0 pc 7 -pc 4 pc 3 -pc 0 pb 7 -pb 0 d 7 -d 0 control word #1 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 10000001 a c? b 8 4 4 8 pa 7 -pa 0 pc 7 -pc 4 pc 3 -pc 0 pb 7 -pb 0 d 7 -d 0 control word #2 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 10000010 a c? b 8 4 4 8 pa 7 -pa 0 pc 7 -pc 4 pc 3 -pc 0 pb 7 -pb 0 d 7 -d 0 control word #3 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 10000011 a c? b 8 4 4 8 pa 7 -pa 0 pc 7 -pc 4 pc 3 -pc 0 pb 7 -pb 0 d 7 -d 0 control word #4 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 10001000 a c? b 8 4 4 8 pa 7 -pa 0 pc 7 -pc 4 pc 3 -pc 0 pb 7 -pb 0 d 7 -d 0 control word #5 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 10001001 a c? b 8 4 4 8 pa 7 -pa 0 pc 7 -pc 4 pc 3 -pc 0 pb 7 -pb 0 d 7 -d 0 control word #6 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 10001010 a c? b 8 4 4 8 pa 7 -pa 0 pc 7 -pc 4 pc 3 -pc 0 pb 7 -pb 0 d 7 -d 0 control word #7 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 10001011 a c? b 8 4 4 8 pa 7 -pa 0 pc 7 -pc 4 pc 3 -pc 0 pb 7 -pb 0 d 7 -d 0
iN82C55AN 10 control word #8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 10010000 a c? b 8 4 4 8 pa 7 -pa 0 pc 7 -pc 4 pc 3 -pc 0 pb 7 -pb 0 d 7 -d 0 control word #9 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 10010001 a c? b 8 4 4 8 pa 7 -pa 0 pc 7 -pc 4 pc 3 -pc 0 pb 7 -pb 0 d 7 -d 0 control word #10 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 10010010 a c? b 8 4 4 8 pa 7 -pa 0 pc 7 -pc 4 pc 3 -pc 0 pb 7 -pb 0 d 7 -d 0 control word #11 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 10010011 a c? b 8 4 4 8 pa 7 -pa 0 pc 7 -pc 4 pc 3 -pc 0 pb 7 -pb 0 d 7 -d 0 control word #12 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 10011000 a c? b 8 4 4 8 pa 7 -pa 0 pc 7 -pc 4 pc 3 -pc 0 pb 7 -pb 0 d 7 -d 0 control word #13 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 10011001 a c? b 8 4 4 8 pa 7 -pa 0 pc 7 -pc 4 pc 3 -pc 0 pb 7 -pb 0 d 7 -d 0 control word #14 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 10011010 a c? b 8 4 4 8 pa 7 -pa 0 pc 7 -pc 4 pc 3 -pc 0 pb 7 -pb 0 d 7 -d 0 control word #15 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 10011011 a c? b 8 4 4 8 pa 7 -pa 0 pc 7 -pc 4 pc 3 -pc 0 pb 7 -pb 0 d 7 -d 0
iN82C55AN 11 operating modes mode 1 (strobed input/output) . this functional configuration provi des a means for transferring i/o data to or from a specified port in conjunc tion with strobes or ?handshaking? signals. in mode 1, port a and port b use the lines on port c to generate or accept these ?handshaking? signals. mode 1 basic functional definitions: ? two groups (group a and group b). ? each group contains one 8-bit dat a port and one 4-bit control/data port. ? the 8-bit data port can be either input or output ? both inputs and outputs are latched. ? the 4-bit port is used for control and status of the ? 8-bit data port. input control signal definition stb (strobe input). a ?low? on this input loads data into the input latch. ibf (input buffer full f/f) a ?high? on this output indicates that the data has been loaded into the input latch; in essence, an acknowledgement. ibf is set by stb input being low and is reset by the rising edge of the r d input. intr (interrupt request) a ?high? on this output can be used to interrupt the cp u when an input device is requesting service. intr is set by the stb is a ?one?, ibf is a ?one? and inte is a ?one?. it is reset by the falling edge of r d . this procedure allows an input device to r equest service from the cpu by simp ly strobing its data into the port. inte a controlled by bit set/reset of pc 4 . inte b controlled by bit set/reset of pc 2 control word d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 10111/0xxx pc 6,7 1 = input 0 = output pa 7 -pa 0 8 pc 4 pc 5 pc 3 inte a pc 6,7 2 stb a ibf a intr a rd mode 1 (port a) control word d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1xxxx1 1x pb 7 -pb 0 8 pc 2 pc 1 pc 0 inte b stb b ibf b intr b rd mode 1 (port b) figure 8. mode 1 input
iN82C55AN 12 t st t sib t sit t rib t rit t ph t ps stb ibf intr rd input from peripheral figure 9. mode 1 (strobed input) output control signal definition obf (output buffer full f/f). the obf output will go ?low? to indicate t hat the cpu has written data out to the specified port. the obf f/f will be set by the rising edge of the wr input and reset by ack input being low. ack (acknowledge input). a ?low? on this input informs the in82c55a n that the data from port a or port b has been accepted. in essence, a response from the per ipheral device indicating t hat it has received the data output by the cpu. intr (interrupt request). a ?high? on this output can be used to interrupt the cpu when an output device has accepted data transmitted by the cpu. intr is set when ack is a ?one?, obf is a ?one? and inte is a ?one?. it is reset by the falling edge of wr . inte a controlled by bit set/reset of pc 6 . inte b controlled by bit set/reset of pc 2 . control word d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 10101/0xxx pc 6,7 1 = input 0 = output pa 7 -pa 0 8 pc 6 pc 7 pc 3 inte a pc 4,5 2 ack a obf a intr a w r mode 1 (port a) control word d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1xxxx1 0x pb 7 -pb 0 8 pc 2 pc 1 pc 0 inte b ack b obf b intr b w r mode 1 (port b) figure 10. mode 1 output
iN82C55AN 13 t aob t wit t ak t ait t wb output ac k intr obf wr t wob figure 11. mode 1 (strobed output) combinations of mode 1 port a and port b can be individually defined as input or output in mode 1 to support a wide variety of strobed i/o applications. control word d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 10111/010x pc 6,7 1 = input 0 = output pa 7 -pa 0 8 pc 4 pc 5 pc 6,7 pb 7 -pb 0 2 stb a ibf a intr a w r pc 3 pc 1 pc 2 obf b ack b intr b pc 0 8 rd port a ? strobed input port b ? strobed output control word d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 10101/011x pc 4,5 1 = input 0 = output pa 7 -pa 0 8 pc 7 pc 6 pc 4,5 pb 7 -pb 0 obf a intr a w r pc 3 pc 2 pc 1 stb b ibf b intr b pc 0 8 rd port a ? strobed output port b ? strobed input 2 ac k a figure 12. combinations of mode 1 operating modes mode 2 (strobed bidirectional bus i/o). this functional configuration pr ovides a means for communicating with a peripheral device or structure on a singl e 8-bit bus for both transmitting and receiving data (bidirectional bus i/o). ?handshaking? signals are provided to maintain proper bus flow discipline in a similar manner to mode 1. interrupt generation and enabl e/disable functions are also available. mode 2 basic functional definitions: ? used in group a only. ? one 8-bit, bi-directional bus port (port a) and a 5- bit control port (port c). ? both inputs and outputs are latched. ? the 5-bit control port (port c) is used for control and status for the 8-bit, bi-dir ectional bus port (port a). bidirectional bus i/o control signal definition intr (interrupt request). a high on this output can be used to in terrupt the cpu for input or output operations. output operations obf (output buffer full) . the obf output will go ?low? to indicate that the cpu has written data out to port a.
iN82C55AN 14 ack (acknowledge). a ?low? on this input enables the tri-state out put buffer of port a to send out the data. otherwise, the output buffer will be in the high impedance state. inte 1 (the inte flip-flop associated with obf ). controlled by bit set/reset of pc 6 . input operations stb (strobe input). a ?low? on this input loads data into the input latch. ibf (input buffer full f/f) . a ?high? on this output indicates that data has been loaded into the input latch. inte 2 (the inte flip-flop associated with ibf). controlled by bit set/reset of pc 4 . control word d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 1 x x x 1/0 1/0 1/0 pc 2-0 1 ? input 0 ? output port b 1 ? input 0 ? output group b 1 ? input 0 ? output figure 13. mode control word pa 7 -pa 0 pc 6 pc 7 pc 3 inte 1 pc 2-0 3 ack a obf a intr a w r pc 5 pc 4 inte 2 ibf a stb a rd figure 14. mode 2
iN82C55AN 15 t wob t aob t ak t st t sib t ps t ad t kd t ph t rib wr obf ack intr stb ibf peripheral bus rd data from cpu to iN82C55AN data from peripheral to iN82C55AN data from iN82C55AN to peripheral data from iN82C55AN to 8080 figure 15. mode 2 (bidirectional) note: any sequence where wr occurs before ack , and stb occurs before rd is permissible. ( wr ack mask obf rd stb mask ibf intr ? ? ? + ? ? ? = )
iN82C55AN 16 control word d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 11xxx011/0 pc 2-0 1 = input 0 = output pa 7 -pa 0 8 pc 7 pc 6 pc 2-0 pb 7 -pb 0 3 obf a ack a intr a w r pc 3 pc 4 pc 5 stb a ibf a 8 rd mode 2 and mode 0 (input) control word d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 11xxx001/0 pc 2-0 1 = input 0 = output pa 7 -pa 0 8 pc 7 pc 6 pc 2-0 pb 7 -pb 0 3 obf a ac k a intr a w r pc 3 pc 4 pc 5 stb a ibf a 8 rd mode 2 and mode 0 (output) control word d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 11xxx10x pa 7 -pa 0 8 pc 7 pc 6 pb 7 -pb 0 obf a ac k a intr a w r pc 3 pc 4 pc 5 stb a ibf a 8 rd mode 2 and mode 1 (output) pc 1 pc 2 obf b ack b intr b pc 0 control word d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 11xxx11x pa 7 -pa 0 8 pc 7 pc 6 pb 7 -pb 0 obf a ac k a intr a w r pc 3 pc 4 pc 5 stb a ibf a 8 rd mode 2 and mode 1 (input) pc 1 pc 2 stb b ibf b intr b pc 0 figure 16. mode 1/4 combinations mode definition summary mode0 mode1 mode2 in out in out group a only pa 0 in out in out ? pa 1 in out in out ? pa 2 in out in out ? pa 3 in out in out ? pa 4 in out in out ? pa 5 in out in out ? pa 6 in out in out ? pa 7 in out in out ? pb 0 in out in out - pb 1 in out in out - pb 2 in out in out - mode 0 pb 3 in out in out - or pb 4 in out in out - mode1 pb 5 in out in out - only pb 6 in out in out - pb 7 in out in out - pc 0 in out intr b intr b i/0 pc 1 in out ibf b obf b i/o pc 2 in out stb b ack b i/o pc 3 in out intr a intr a intr a pc 4 in out stb a i/o stb a pc 5 in out ibf a i/o ibf a pc 6 in out i/o ack a ack a pc 7 in out i/o obf a obf a
iN82C55AN 17 special mode combination considerations there are several combinations of modes possible. for any combination, some or all of the port c lines are used for control or status. the remaining bits are either inputs or outputs as defined by a ?set mode? command. during a read of port c, the state of all the port c lines, except the ack and stb lines, will be placed on the data bus. in place of the ack and stb line states, flag status will appear on the data bus in the pc 2 , pc 4 , and pc 6 bit positions as illustrated by figure 18. through a ?write port c? command, only the port c pins programmed as outputs in a mode 0 group can be written. no other pins can be affected by a ?write port c? command, nor can the interrupt enable flags be accessed. to write to any port c output progra mmed as an output in a mode 1 group or to change an interrupt enable flag, the ?set/reset port c bit? command must be used. with a ?set/reset port c bit? command, any port c line programmed as an output (including intr, ibf and obf ) can be written, or an interrupt enable flag can be ei ther set or reset. port c lines programmed as inputs, including ack and stb lines, associated with port c are not affected by a ?set/reset port c bit? command. writing to the corresponding port c bit positions of the ack and stb lines with the ?set/reset port c bit? command will affect the group a and group b interrupt enable flags, as illustrated in figure 18. current drive capability any output on port a, b or c can sink or source 2.5ma. this feature allows the iN82C55AN to directly drive darlington type drivers and high-voltage displays t hat require such sink or source current. reading port c status in mode 0, port c transfers data to or from the peripheral device. when the iN82C55AN is programmed to function in modes 1 or 2, port c generates or acc epts ?hand-shaking? signals wi th the peripheral device. reading the contents of port c allows the programmer to test or verify the ?status? of each peripheral device and change the program flow accordingly. there is no special instruction to read the status info rmation from port c. a normal read operation of port c is executed to perform this function. input configuration d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 i/o i/o ibf a inte a intr a inte b ibf b intr b group a group b output configuration d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 obf a inte a i/o i/o intr a inte b obf b intr b group a group b figure 17a. mode 1 status word format d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 obf a inte 1 ibf a inte 2 intr a group a group b (defined by mode 0 or mode 1 selektion) figure 17b. mode 2 status word format
iN82C55AN 18 interrupt enable flag position alternate inte b pc 2 ack b (output mode 1) or stb b (input mode 1) inte a2 pc 4 stb a (input mode 1 or mode 2) inte a1 pc 6 ack a (output mode 1 or mode 2) figure 18. interrupt enable flags in modes 1 and 2 absolute maximum ratings* ambient temperature under bias 0 o c to + 70 o c storage temperature - 65 o c to + 150 o c supply voltage - 0.5 to + 8.0v operating voltage + 4v to + 7v voltage on any input gnd-2v to + 6.5v voltage on any output gnd-0.5v to v cc + 0.5v power dissipation 1watt notice: this is a production data sheet. the specifications are s ubject to change without notice. *warning: stressing the device beyond the ?absolut e maximum ratings? may cause permanent damage. these are stress ratings only. operation beyond the ?operating conditions? is not recommended and extended exposure beyond the ?operating condi tions? may affect device reliability. d.c. characteristics t a = 0 o cto70 o c, v cc =+5v 10%, gnd = 0v (t a =-40 o c to +85 o c for extended temperature) symbol parameter min max units test conditions v il input low voltage -0.5 0.8 v v ih input high voltage 2.0 v cc v v ol output low voltage 0.4 v i ol = 2.5ma v oh output high voltage 3.0 v i oh =-2.5ma v cc - 0.4 v i oh =-100a i il input leakage current 1 a v in = v cc to 0v (note 1) i ofl output float leakage current 10 a in = v cc to 0v (note 2) i dar darlington drive current 2.5 (note 4) ma ports a,b,c r ext = 500 ? v ext = 1.7v i phl port hold low leakage current +50 +300 a v out = 1.0v port a only i phh port hold high leakage current -50 -300 a v out = 3.0v ports a,b,c i phlo port hold low overdrive current -350 a v out = 0.8v i phho port hold high overdrive current +350 a v out = 3.0v i cc v cc supply current 10 ma (note 3) i ccsb v cc supply current- standby 10 a v cc = 5.5v v in = v cc or gnd port conditions if i/p = open/high o/p = open only with data bus = high/low cs = high reset = low pure inputs = low/high notes:
iN82C55AN 19 1. pins a1, a0, cs, wr, rd, reset 2. data bus; ports b, c 3. outputs open. 4. limit output current to 4.0ma. capacitance t a = 25 o c, v cc = gnd = 0v symbol parameter min max units testconditions c in input capacitance 10 pf unmeasured pins c i/o i/o capacitance 20 pf returned to gnd f c = 1mhz(5) note: 5. sampled not 100% tested. a.c. characteristics t a = 0 o to 70 o c, v cc = +5v 10%, gnd = 0v t a = -40 o c to +85 o c for extended temperature bus parameters read cycle symbol parameter min max units test conditions t ar address stable before rd _ 0 ns t ra address hold time after rd _ 0 ns t rr rd pulse width 150 ns t rd data delay from rd _ 120 ns t df rd _ to data floating 10 75 ns t rv recovery time between rd / wr 200 ns write cycle symbol parameter min max units test conditions t aw address stable before wr _ 0 ns t wa address hold time after wr _ 20 ns portsab 20 ns portc t ww wr pulse width 100 ns t dw data setup time before wr _ 100 ns t wd data hold time after wr _ 30 ns portsab 30 ns portc
iN82C55AN 20 other timings symbol parameter min max units test conditions t wb wr = 1 to output 350 ns t lr peripheral data before rd 0 ns t hr peripheral data after r d 0 ns t ak ack pulse width 200 ns t st stb pulse width 100 ns t ps per. data before stb high 20 ns t ph per. data after stb high 50 ns t ad ack = 0 to output 175 ns t kd ack = 1 to output float 20 250 ns t wob wr = 1 to obf = 0 150 ns t aob ack = 0 to obf = 1 150 ns t sib stb = 0 to ibf = 1 150 ns t rib r d = 1 to ibf = 0 150 ns t rit r d = 0 to intr = 0 200 ns t sit stb = 1 to intr = 1 150 ns t ait ack = 1 to intr = 1 150 ns t wit wr = 0 to intr = 0 200 ns see note1 t res reset pulse width 500 ns see note2 note 1. intr_ may occur as early as wr _. 2. pulse width of initial reset pulse after power on must be at least 50sec. subsequent reset pulses may be 500ns minimum. the output ports a b or c may glit ch low during the reset pulse but all port pins will be held at a logic ?one? level after the reset pulse. write timing a 0-1 ,cs data bus wr t wa t dw t aw t ww t wd
iN82C55AN 21 read timing a 0-1 ,cs data bus rd t ra t dr t ar t rr t rd high impedance high impedance valid a.c. testing input, output waveform a.c. testing load circuit 2.4 0.45 2.0 0.8 2.0 0.8 test points c l =150pf a.c. testing inputs are driven at 2.4v for a logic 1 and 0.45v for a logic 0 timing measurements are made at 2.0v for a logic 1 and 0.8 for a logic 0. a.c. testing load circuit device under test *v ext is set at various voltages during testing to guarantee the specification. c l includes jig capacitance. v ext * c l =150pf

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